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Submission data

Full nameMANE
DescriptionThe propose a novel stereo matching algorithm with fuzzy logic and also implement it on an FPGA embedded system. We try to select the best window size of SAD for each pixel by leveraging fuzzy logic.
Programming language(s)VHDL
HardwareCyclone V 5CSEBA6U23I7 FPGA
Submission creation date9 Sep, 2020
Last edited15 Sep, 2020

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Infoalllakes. 1llakes. 1ssand box 1lsand box 1sstora. room 1lstora. room 1sstora. room 2lstora. room 2sstora. room 2 1lstora. room 2 1sstora. room 2 2lstora. room 2 2sstora. room 3lstora. room 3stunnel 1ltunnel 1stunnel 2ltunnel 2stunnel 3ltunnel 3s
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